for EPD monitoring

List of EPD Runs and Boards with issues

Trying to make a list of all of the channels that we have problems with, when it happened and where they are located. For example of what the issue is, see

BUR Spin Cold-QCD Highlights

 

Trigger Board Meeting for Run18

2018-03-19 13:00
America/New York
Monday, 19 March 2018
BNL Physics 1-224 and Bluejeans 818117372, at 17:00 (GMT), duration : 00:00
 - Run status and progress
 - Trigger optimization
 - running condition
 - HF, MTD, UPC triggers: goal vs luminosity  
 - EPD trigger
 - AoB

Setting bias voltages for 2018 run (Bias scan)


Note: The numbers that I give below are Vset, not the true Vbias seen by the SiPM.  The relationship betw

systematic

 

NICA Days 2017 proceedings - final

NICA Days 2017 proceedings - final

2018 Moriond QCD Talk

 15 minutes, plus 5 for questions.

Forward Tracking Progress


Talk time : 16:40, Duration : 00:20

iTPC Integration DIscussion


Talk time : 16:00, Duration : 00:40

S&C Offline Software

2018-03-15 16:00
2018-03-15 17:15
America/New York
Thursday, 15 March 2018
1-189, SRN, at 20:00 (GMT), duration : 01:15
SRN ID: 1096183

EVO Phone Bridge Telephone Numbers:
---------------
- USA (BNL, Upton, NY)
+1 631 344 6100

- USA (Caltech, Pasadena, CA)
+1 626 395 2112
TimeTalkPresenter
16:00iTPC Integration DIscussion ( 00:40 ) 0 files
16:40Forward Tracking Progress ( 00:20 ) 1 file

First EPD Physics of 2018

The very first physics run of the EPD is 19074053.  This run includes the proper gate settings and bias settings.

A one figure summary:

4 Strange Channels in EPD

So as we have been finalizing Vbias and the gate settings and so forth, I noticed that the first 4 channels have some odd behavior in the ADC plots.

HF minutes 2018/03/15

1) Run16 fastsim and D0 - Xiaolong Chen

abstract for CALOR 2018

 

abstract for CALOR 2018

 

J/psi polarization measurement in pp at 200 GeV

 

Run16 fast simualtion and D0

 

NICA Days 2017 proceedings v4

NICA Days 2017 proceedings v4

EPD timing scan for Run 2018

Executive Summary:

Gate-delay study finds that maximizing average signal integration (i.e. largest ADC value for MIP peak) is obtained for