Bad tiles or electronics - Run 2025

Under:
10 June 2025

From scrolling through the final panel on each page of this big pdf from the gate scan (see the blog for details), Mike sees:

Dead - the highlighted ones may be a QT daughter card
  • East PP07 TT22 - Cr1 Sl2 Ch30 : ADC looks bad, and colors in shift monitoring plots are odd
  • West PP01 TT06 - Cr2 Sl8 Ch24 : super dead. We know it also from 7 pattern, no ADC
  • East PP07 TT18 - Cr3 Sl4 Ch24  : ugly ADC
  • West PP02 TT08 - Cr3 Sl4 Ch25 : empty ADC
  • West PP02 TT10 - Cr3 Sl4 Ch26 : empty ADC
  •  
Very bad MIP resolution
  • East PP07 TT24 - Cr1 Sl4 Ch8 : ugly ADC
  • East PP01 TT01 - Cr2 Sl0 Ch24 : ugly ADC
  • West PP02 TT02 - Cr2 Sl10 Ch8 - might be okay : ugly ADC
  • West PP02 TT12 - Cr2 Sl14 Ch0 : not bad ADC
  • West PP02 TT04 - Cr3 Sl4 Ch8 : ugly ADC
  • West PP02 TT14 - Cr3 Sl4 Ch9 : not bad ADC
  • West PP02 TT01 - Cr3 Sl8 Ch9 : ugly ADC
  • West PP02 TT06 - Cr4 Sl8 Ch8 : ugly ADC
  • West PP02 TT20 - Cr4 Sl12 Ch28 - might be okay : ADC looks ok!

===========================================
June 16th 2025
Maria's edit will be in
blue;
I used the 26166044 run to validate adc and tac. Plots attached.

More: in yellow new tiles in comparison with above

NO TAC:
E  PP7 TT3 : only TAC missing, ADC looks ok
W PP1 TT6 : dead
W PP4 TT6 :  only TAC missing, ADC looks ok

NO ADC:

W PP01 TT06 : dead
E PP07 TT03 : empty ADC
W PP02 TT08 : empty ADC, already mentioned above
W PP02 TT10: empty ADC, already mentioned above


Comment: I would shift Vset for W PP08 TT31