Output files of inner hybrid (v2.1)

 output files of inner hybrid (v2.1)

Output files of outer hybrid (v2.2)

Modification: Locations of the APV25 chips on outer hybrid

Weekly Meeting (Oct. 21)

-ZZ: paper proposal 
- Xiaoxuan: pAu calibration updates
- Minghui: suggest to start preparation for Run-17 calibration

27GeV Proton nHitsFit Comparison

 

qm2019 Support Material

TPC Run 17 pp500 SC&GL

Final Run 17 pp510 SC&GL Calibration used in Run17 P20ia reproduction: pdf

q2 v2 dependence of the R correlator

 

v1 analysis with AuAu@27 GeV

This is the continuous work of what Mike did over one year ago with the fast offline data.

FST Test Stand Cable PO Documentation from PO 0000363726

 

JetCorr 191018

 

HF minutes 2019/10/17

qm19poster

 

Materials for Discussion

S&C Offline Software

2019-10-17 16:00
2019-10-17 17:00
America/New York
Thursday, 17 October 2019
1-189, at 20:00 (GMT), duration : 01:00

Offline roundtable.
TimeTalkPresenter
16:00Materials for Discussion ( 00:20 ) 0 files

Run 17 beam positions

In hopes of finding some causal correlation with fill-by-fill variations in the high-pT ratios of global tracks in Run 17 pp510 data, I looked for possible clues in the beam position data.<

STAR Forward Silicon Tracker Meeting

2019-10-18 10:30
2019-10-18 11:30
America/New York
Friday, 18 October 2019
https://bluejeans.com/101020434 , at 14:30 (GMT), duration : 01:00
Minutes from meeting

 



Would it be possible to have a meeting (remote) on this tomorrow Friday pref in the morning.   (10/18)

 
-discussion

a) what went wrong here (my interpretaation of mike e-mail)

b) what is the correct design

c) who/when will it be done

c) signoff before we proceed as its clearly not ready for production as mike put the assembly on hold

 

n  Need to update documentationoduction.

Mike’s e-mail

 

Not sure who to address this to - I've asked the vendor to hold off on putting the test stand cables on the T-board, as I've noticed some discrepancies.  (Very good).

 

The attached Excel spreadsheet from Steve Valentino was used when ordering the test stand cables. Each wire/pair is labeled using the "Via Ref Des" column, in column "G", which corresponds to the D-Sub connector pin listed in column A.

 

When compared to the schematic for T-Board V2.0 the Via Ref Des is incorrect - the correct values according to the schematic are listed in Column I. This affected only OUT0 through OUT3. They are in reverse order, and some also have polarity reversed. This affects the first V2.0 test T-Boards we assembled.

 

Zhenyu, I believe these were sent to you, if so just be aware.  

 

When compared to the T-Board V2.1 the Via Ref Des is incorrect - the correct values according to the schematic are listed in Column J. This affected only OUT0 through OUT2. OUT3 is correctly labeled. OUT0 through OUT2 all have polarity reversed.

 

I do not know the reason for the Via Ref Des changes between schematic/pcb revisions, or why the spreadsheet appears incorrect for both V2.0 and V2.1

 

I would appreciate it if someone could tell me if my assumption regarding the correct labeling for the cable should be what I’ve listed in Column J, and if not let me know what it should be.

 

Who designed the version 2.1. Who double checked it?

We seem to be lacking some QA process.

 

 

10/18 - message

 After checking all versions for T-board, I find that Column G is related to the original version which wasn't produced, and Column I related to T2.0
 Column J related to T2.1.
 The changes for different versions are just for easy and quick routing.
 I'm sorry I didn't figure it out clearly when I updated the design.
 Is it possible to update the mapping now?

 


 

 

 

 

191017 HF Weekly Meeting

 

Updated errors to c->e v1 and b,c->e RAA

QM_slides_focusmeet

 

scp through an intermediate node - using a tunel

OK so I already provided help for tunneling for special services (Web access for example - see Creating an SSH tunnel in Linux ) but was asked a few times how to copy files in and out of BNL or in between enclave.