NOTE: All sheets are not complete...all sheets in this update are still W.I.P.

Sheet 1 MAIN:

This will be mainly the one wire bus distrobution from the FPGA to the FP connectors (DB15) that go to the FEE cards, including opto driver transceiver circuit.

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Sheet 2 POWER:

Right now this is mostly local power rails.

1.2v LDO --> FPGA VCC_INT

3.3v LDO --> FPGA VCC_AUX

3.3v LDO --> FPGA VCCO_3_3

1.8v LDO --> 16 meg platform flash PROM

Power to FEE cards.

This still needs to be determined as I do not have specifics other than voltage and current requierments.

Current ~ 40ma / FEE --> +6Vdc,  do not have current spec for -6Vdc

Voltages:

+6 Vdc 
- 6 Vdc
-90 Vdc (SiPM bias)

Power Requierments questions???

Do we have local regulation on FEE +/- 6VDC ?

What is the tolerance (+/- 6VDC and -90Vdc) for voltage input to FEE card?

GV is still considering the APD 90v module for use as SiPM bias source --> need to know outcome?

I was considering using an ACOPIAN switching DC popwer supply to provide ~ 7VDC to the TUFF box.

http://www.acopian.com/store/8y-%281%29.aspx?min=3.3&max=48

If the FEE cards have local regulation....we feed the ACOPIAN directly to the FEE cards --> should be O.K. to use REMOTE SENSE here too.

I could then use FET switches to switch the power ON/OFF to the FEE group.

Same thing with the -90 Vdc supply.

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Sheet 3 FPGA CONFIG:

FPGA cofigs local from 16Meg Xilinx platform flash

SBC connections provided for remote configuration via JTAG as per TCD card

JTAG header

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Sheet 4 SBC

Ethernet connector with activity LED's

16 bit data and control bus to FPGA as per TCD card