Updates for TPC iFEE Development CCA:

 

As per meeting from 1/10/2014

 

SAMPA data loop-back connections (SAMPA_DATA, sheet 5)
 

-          There is a loopback for 1 SAMPA chip, all vector data and discrete lines for SAMPA communications

-         
For example: Differential pairs, SAMPA_D_N0 and SAMPA_D_P0, connects from FPGA BANK-1 (SAMPA DATA BANK) to BANK-2 à(TEST BANK FOR SAMPA DATA)

BANK 2 test header, changed to 16 BIT

 

Power Sequencing:

                Although the POR for the SPARTAN 6 handles power on reset management (waits for all voltages to stabilize), I included power sequence to make certain that the platform flash chip is ready for configuration. I have an RC circuit buffered that enables the LDO’s after the flash chip is powered for    ~1msec.

 

Added additional voltage rail indicator LED’s

-          All the rails have a yellow LED indicating power available; the digital and analog voltages in from RDO have green pilot LED’s.

 

RGB LED, PN: MSL0201RGB1

-          I added a right angle RGB LED. {3mm x .43mm}. It should make a very cool indicator. We can do a strobe effect and other cool things. Different colors can mean different operating mode, sort of like we do with DAQ display cards.

 

RDO interconnect:

-          All signals between the FEE and RDO are shown on sheet 2 of the schematic.

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MGT gigabit buffer, SYS5621R:

-          Added CML HS transceiver/ buffer for transmit pair to RDO.

-          Also, we have an option to use “402” capacitor coupling if required

-          This required adding a small (100ma) regulator for this chip since it operates internal (VCC = 2.5v). The I/O voltage is selectable from 1.2 to 2.5 VDC.